Alessandro Barenghi

Latest

An Efficient and Unified RTL Accelerator Design for HQC-128, HQC-192, and HQC-256
Review of Policy-as-code Approaches to Manage Security and Privacy Conditions in Edge and Cloud Computing Ecosystems
A High Efficiency Hardware Design for the Post-Quantum KEM HQC
A Quantum Circuit to Execute a Key-Recovery Attack Against the DES and 3DES Block Ciphers
A Versatile and Unified HQC Hardware Accelerator
Optimizing Quantum Circuit Synthesis with Dominator Analysis
Performance and Efficiency Exploration of Hardware Polynomial Multipliers for Post-Quantum Lattice-Based Cryptosystems
Quantum Circuit Design for the Lee-Brickell Based Information Set Decoding
A Non Profiled and Profiled Side Channel Attack Countermeasure through Computation Interleaving
An Efficient Unified Architecture for Polynomial Multiplications in Lattice-Based Cryptoschemes
Metis: An Integrated Morphing Engine CPU to Protect Against Side Channel Attacks
A comprehensive analysis of constant-time polynomial inversion for post-quantum cryptosystems
A Novel Regular Format for X.509 Digital Certificates
A fault-based secret key retrieval method for ECDSA: analysis and countermeasure
A note on fault attacks against deterministic signature schemes
A privacy-preserving encrypted OSN with stateless server interaction: the Snake design
A combined design-time/test-time study of the vulnerability of sub-threshold devices to low voltage fault attacks
A Multiple Equivalent Execution Trace Approach to Secure Cryptographic Embedded Software
A Fault Induction Technique Based on Voltage Underfeeding with Application to Attacks against AES and RSA
A Code Morphing Methodology to Automate Power Analysis Countermeasures
A novel fault attack against ECDSA
A FPGA coprocessor for the cryptographic Tate pairing over Fp