Latest
- A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs
- An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
- A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS
- Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms
- Design-time methodology for optimizing mixed-precision CPU architectures on FPGA
- FPGA-Based Design and Implementation of a Code-Based Post-quantum KEM
- Functional ISS-Driven Verification of Superscalar RISC-V Processors
- ML-Assisted Attack Detection on NoC-Based Many-Cores Through On-Chip Traffic Monitoring
- A survey on run-time power monitors at the edge
- An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE
- Hardware and Software Support for Mixed Precision Computing: A Roadmap for Embedded and HPC Systems
- HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs
- Cost-effective fixed-point hardware support for RISC-V embedded systems
- Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems
- FPGA implementation of BIKE for quantum-resistant TLS
- Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators
- On the Effectiveness of True Random Number Generators Implemented on FPGAs
- On the use of hardware accelerators in QC-MDPC code-based cryptography
- An FPU design template to optimize the accuracy-efficiency-area trade-off
- Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography
- Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials
- HEAP Lab Team wins the “Switch to Product Innovation Challenge 2019”!
- Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions