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Ruggero Susella
Latest
A High Efficiency Hardware Design for the Post-Quantum KEM HQC
A Versatile and Unified HQC Hardware Accelerator
Performance and Efficiency Exploration of Hardware Polynomial Multipliers for Post-Quantum Lattice-Based Cryptosystems
A Flexible ASIC-Oriented Design for a Full NTRU Accelerator
An Efficient Unified Architecture for Polynomial Multiplications in Lattice-Based Cryptoschemes
A fault-based secret key retrieval method for ECDSA: analysis and countermeasure
A novel fault attack against ECDSA
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