Hardware Design

The computer architecture research area describes the rules and techniques to organize and implement the functionality of a computing system. In our group, we focus on the design of methodologies and architectures for current and future multi-cores, ranging from embedded to high performance processors. In particular, the research activities are organized in three different branches:

• Energy-Performance Optimization of the Uncore in Multi-cores: the research of the group in this area aims at designing and implementing novel coherence protocols, cache hierarchy as well as on-chip interconnects for new generations of multi-cores
• Designing Secure Computer Architectures: the research group focuses on the design and implementation of novel architecture design strategies for both embedded CPUs and cryptographic hardware accelerators to face the so-called side-channel attacks (new security threats that exploit the possibility to correlate the physical information extracted form the device with the actual data-dependent computation in order to extract the secret key)
• Design and Implementation of Power Efficient Embedded Multi-Cores: the research group aims at the design and verification of novel RISC-based microarchitectures for the embedded market segment with a twofold objective. First, explore different microarchitectural solutions for low-power scenarios. Second, provide FPGA-based prototypes to advance the hardware-software co-design for resource allocation and low-power aspects