CONTREX


Date
Oct 1, 2013 — Nov 30, 2016

Up to now, mission & safety critical services of SoS (Systems of Systems) have been running on dedicated and often custom designed HW/SW platforms. In the near future such systems will be accessible, connected with or executed on devices comprising off-the-shelf HW/SW components. Significant improvements have been achieved supporting the design of mixed-critical systems by developing predictable computing platforms and mechanisms for segregation between applications of different criticalities sharing computing resources. Such platforms enable techniques for the compositional certification of applications’ correctness, run-time properties and reliability. CONTREX (Oct 2013 - Nov 2016) will complement these important activities with an analysis and segregation along the extra-functional properties real-time, power, temperature and reliability.

These properties will be a major cost roadblocks when:

  • scaling up the number of applications per platform and the number of cores per chip
  • in battery powered devices or
  • switching to smaller technology nodes

CONTREX will enable energy efficient and cost aware design through analysis and optimisation of real-time, power, temperature and reliability with regard to application demands at different criticality levels. To reinforce European leadership and industrial competiveness the CONTREX approach will be integrated into existing model-based design methods that can be customized for different application domains and target platforms. CONTREX will focus on the requirements derived from the automotive, aeronautics and telecommunications domain and evaluate its effectiveness and drive integration into existing standards for the design and certification based on three industrial demonstrators. Valuable feed-back to the industrial design practice, standards, and certification procedures is pursued.Up to now mission & safety critical services of SoS (Systems of Systems) have been running on dedicated and often custom designed HW/SW platforms. In the near future such systems will be accessible, connected with or executed on devices comprising off-the-shelf HW/SW. Our economic goal is to improve energy efficiency by 20 % and to reduce cost per system by 30 % due to a more efficient use of the computing platform.

William Fornaciari
William Fornaciari
Associate Professor

William Fornaciari has published six books and over 200 papers, earning five best paper awards, an IEEE certification, and three international patents on low power design. Since 1997, he has participated in 18 EU-funded projects. His research focuses on multi/many-core architectures, NoC, low power design, and more.

Gianluca Palermo
Gianluca Palermo
Full Professor

Gianluca Palermo received the M.Sc. degree in Electronic Engineering in 2002, and the Ph.D degree in Computer Engineering in 2006 from Politecnico di Milano. He is currently an associate professor at Department of Electronics and Information Technology in the same University. Previously he was also consultant engineer in the Low Power Design Group of AST – STMicroelectronics working on network on-chip and research assistant at the Advanced Learning and Research Institute (ALaRI) of the Università della Svizzera italiana (Switzerland). His research interests include design methodologies and architectures for embedded and HPC systems, focusing on AutoTuning aspects.