MANGO


Date
Oct 1, 2015 — Sep 30, 2018

The essential objective of MANGO (Oct 2015 - Sept 2018) is to achieve extreme resource efficiency in future QoS-sensitive HPC through ambitious cross-boundary architecture exploration. The research will investigate the architectural implications of the emerging requirements of HPC applications, aiming at the definition of new-generation high-performance, power-efficient, deeply heterogeneous architectures with native mechanisms for isolation and quality-of-service.

To achieve such ambitious objectives, MANGO will avoid conservative paths. Instead, its disruptive approach will challenge several basic assumptions, exploring new many-core architectures specifically targeted at HPC. The project will involve many different and deeply interrelated mechanisms at various architectural levels:

  • Heterogeneous computing cores
  • Memory architecture
  • Interconnect
  • Runtime resource management
  • Power monitoring and cooling
  • Programming models

In particular, to gain a system-wide understanding of the deep interplay of mechanisms along the PPP axes, MANGO will explore holistic proactive thermal and power management aimed at energy optimization, creating a hitherto inexistent link between hardware and software effects and involving all layers modeling in HPC server, rack, and datacenter conception. Ultimately, the combined interplay of the multi-level innovative solutions brought by MANGO will result in a new positioning in the PPP space, ensuring sustainable performance as high as 100 PFLOPS for the realistic levels of power consumption (<15MWatt) delivered to QoS-sensitive applications in large-scale capacity computing scenarios. Particularly relevant for current European HPC strategies, the results achieved by the project will provide essential building blocks at the architectural level enabling the full realization of the long-term objectives foreseen by the ETP4HPC strategic research agenda.

This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 671668

William Fornaciari
William Fornaciari
Associate Professor

William Fornaciari has published six books and over 200 papers, earning five best paper awards, an IEEE certification, and three international patents on low power design. Since 1997, he has participated in 18 EU-funded projects. His research focuses on multi/many-core architectures, NoC, low power design, and more.

Giovanni Agosta
Giovanni Agosta
Associate Professor

Giovanni Agosta, Associate Professor at Politecnico di Milano, holds a Laurea in Computer Engineering (2000) and a PhD in Information Technology (2004). His research focuses on compiler-computer architecture interaction, emphasizing performance, energy-efficiency, and security. He has authored 100+ papers, won multiple awards, and participated in 17 EU-funded projects.