RECIPE


Date
May 1, 2018 — Apr 30, 2021

RECIPE (REliable power and time-ConstraInts-aware Predictive management of heterogeneous Exascale systems) is a new FETHPC-02-2017 – Transition to Exascale Computing – project lead by Politecnico di Milano – Dipartimento di Elettronica, Informazione e Bioingegneria with a total funding of 3,285,300 €.

The Project Coordinator is prof. William Fornaciari, the Project Technical Manager is prof. Giovanni Agosta and the duration is 36 months: May 2018 – April 2021. RECIPE, in addition to other running projects of the HEAP Lab (M2DC, MANGO) contributes to positioning of POLIMI as one of the biggest cluster of projects on HPC/Exascale computing in Europe. RECIPE provides: a hierarchical runtime resource management infrastructure optimizing energy efficiency and minimizing the occurrence of thermal hotspots, while enforcing the time constraints imposed by the applications, and ensuring reliability for both time-critical and throughput-oriented computation. A number of goals have been identified, the more relevant are: increase in energy efficiency (performance/watt) of 25% with an improvement of 15% of MTTF due to proactive thermal management; energy-delay product improved up to 25%; 20% reduction of occurring in fault executions with recovery times compatible to real-time performance and full exploitation of available resources under non-saturated conditions. The consortium is aggregating some of the most important players in Europe: POLIMI is providing expertise on resource management and programming models as well as scientific coordination; EPFL, the leading provider of thermal models for HPC; UPV, one of the key innovators in optimized interconnection networks, and CeRICT, providing expertise on accelerators; as well as two supercomputing centers: BSC, one of the leading HPC providers in Europe with the MareNostrum, classed 13th in the Top 500 in June 2017, and PSNC, another Top 500 HPC center in Poland; a research hospital from Switzerland, CHUV, and an SME active in product design and development, IBTS, which provide effective exploitation avenues through industry-based use cases.

William Fornaciari
William Fornaciari
Associate Professor

William Fornaciari has published six books and over 200 papers, earning five best paper awards, an IEEE certification, and three international patents on low power design. Since 1997, he has participated in 18 EU-funded projects. His research focuses on multi/many-core architectures, NoC, low power design, and more.

Giovanni Agosta
Giovanni Agosta
Associate Professor

Giovanni Agosta, Associate Professor at Politecnico di Milano, holds a Laurea in Computer Engineering (2000) and a PhD in Information Technology (2004). His research focuses on compiler-computer architecture interaction, emphasizing performance, energy-efficiency, and security. He has authored 100+ papers, won multiple awards, and participated in 17 EU-funded projects.