Paper-Conference

A framework for Compiler Level statistical analysis over customized VLIW architecture
Very Long Instruction Word (VLIW) application specific processors represent an attractive solution for embedded computing, offering …
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A Meta-Model Assisted Coprocessor Synthesis Framework for Compiler/Architecture Parameters Customization
Hardware coprocessors are extensively used in modern heterogeneous systems-on-chip (SoC) designs to provide efficient implementation of …
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Adaptive routing and dynamic frequency scaling for NoC power-performance optimizations
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An analytical, dynamic, power-performance router model for run-time NoC optimizations
Abstract— Network-on-Chip (NoC) are considered the promi- nent interconnection solution for current and future many-core architectures. …
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A Code Morphing Methodology to Automate Power Analysis Countermeasures
We introduce a general framework to automate the application of countermeasures against Differential Power Attacks aimed at software …
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A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures
The execution of multiple multimedia applications on a modern Multi-Processor System-on-Chip (MPSoC) rises up the need of a Run-Time …
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A Methodology and a Case Study of Dynamic Power Management for Embedded Systems
This paper present the results of a study on Dynamic Power Management (DPM) developed in cooperation between Politecnico di Milano and …
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A PI-based Control Structure as an Operating System Scheduler
Many functions of operating systems are keen to be realised as feedback controllers. Doing so has a non negligible design impact, but …
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A sensor-less NBTI mitigation methodology for NoC architectures
CMOS technology improvement allows to increase the number of cores integrated on a single chip and makes Network-on-Chips (NoCs) a key …
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A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures
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