Paper-Conference

Hardware acceleration of complex machine learning models through modern high-level synthesis
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Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators
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Higher-Level Synthesis: experimenting with MLIR polyhedral representations for accelerator design
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MLIR Loop Optimizations for High-Level Synthesis: a Case Study
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On the Effectiveness of True Random Number Generators Implemented on FPGAs
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On the use of hardware accelerators in QC-MDPC code-based cryptography
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Precision Tuning in Parallel Applications
Nowadays, parallel applications are used every day in high performance computing, scientific computing and also in everyday tasks due …
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The mARGOt autotuning framework design and improvements
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A Complete Quantum Circuit to Solve the Information Set Decoding Problem
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A Multi-Level DPM Approach for Real-Time DAG Tasks in Heterogeneous Processors
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