A combined design-time/test-time study of the vulnerability of sub-threshold devices to low voltage fault attacks

Alessandro Barenghi, Cedric Hocquet, David Bol, Francois Xaviermsc Standaert, Francesco Regazzoni, Israel Koren
January 2014
Cite DOI URL
Type
Journal article
Publication
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
AES; Design Simulation; Fault Attacks; Setup Time Violation; Computer Science (Miscellaneous);