Exploring Manycore Architectures for Next-Generation HPC Systems through the MANGO Approach

Publication
MICROPROCESSORS AND MICROSYSTEMS
Giovanni Agosta
Giovanni Agosta
Associate Professor

Giovanni Agosta, Associate Professor at Politecnico di Milano, holds a Laurea in Computer Engineering (2000) and a PhD in Information Technology (2004). His research focuses on compiler-computer architecture interaction, emphasizing performance, energy-efficiency, and security. He has authored 100+ papers, won multiple awards, and participated in 17 EU-funded projects.

Carlo Brandolese
Carlo Brandolese
Assistant Professor

Carlo Brandolese is a researcher at the Department of Electronics and Information of the Politecnico di Milano and a consultant researcher at Cefriel Research Centre. His research interests are focused on design and low-power methodologies for embedded systems.

William Fornaciari
William Fornaciari
Associate Professor

William Fornaciari has published six books and over 200 papers, earning five best paper awards, an IEEE certification, and three international patents on low power design. Since 1997, he has participated in 18 EU-funded projects. His research focuses on multi/many-core architectures, NoC, low power design, and more.

Simone Libutti
Ph.D. Student
Giuseppe Massari
Assistant Professor
Anna Pupykina
Ph.D. Student
Federico Reghenzani
Federico Reghenzani
Assistant Professor

Federico Reghenzani received his PhD degree from Politecnico di Milano in January 2021. He is currently a researcher working on real-time systems and embedded computing. His research interests are on probabilistic real-time, mixed-criticality systems, fault tolerance, and embedded Linux systems.

Michele Zanella
Ph.D. Student
Davide Zoni
Davide Zoni
Associate Professor

Davide Zoni received the Master Degree in Computer Engineering in 2010 and the Ph.D. in Information Technology in 2014, both from Politecnico di Milano, Italy, where he holds a Post-Doc position at DEIB—Dipartimento di Elettronica Informazione e Bioingegneria. His research interests include RTL design and low-power optimizations for multi-cores with particular emphasis on cache coherence protocols, on-chip interconnect and hardware-based side-channel countermeasures.