A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture

Davide Zoni, Alessandro Barenghi, Gerardo Pelosi, William Fornaciari
January 2018
Cite DOI URL
Type
Journal article
Publication
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
Davide Zoni
Davide Zoni
Associate Professor

Davide Zoni received the Master Degree in Computer Engineering in 2010 and the Ph.D. in Information Technology in 2014, both from Politecnico di Milano, Italy, where he holds a Post-Doc position at DEIB—Dipartimento di Elettronica Informazione e Bioingegneria. His research interests include RTL design and low-power optimizations for multi-cores with particular emphasis on cache coherence protocols, on-chip interconnect and hardware-based side-channel countermeasures.

Alessandro Barenghi
Alessandro Barenghi
Associate Professor

Alessandro Barenghi holds an M.Sc. (2007) and Ph.D. (2011) from Politecnico di Milano. His research focuses on computer, embedded, and network security, particularly applied cryptography. He also works on formal languages and compilers, specifically techniques for parallel parsing using operator precedence grammars.

Gerardo Pelosi
Gerardo Pelosi
Associate Professor

Gerardo Pelosi received the Laurea degree in Telecommunications Engineering in 2003 and the Ph.D. degree in Computer Engineering and Information Technology in 2007 from Politecnico di Milano. His research fields cover (1) the area of information security and privacy including access control models, models for encrypted data management in relational databases, and secure data outsourcing; (2) the area of applied cryptography including side-channel cryptanalysis, system-level attacks, and efficient hardware and software design of cryptographic algorithms; other research interests are in designing security support into computer architectures and the logic synthesis of combinatorial circuits.

William Fornaciari
William Fornaciari
Associate Professor

William Fornaciari has published six books and over 200 papers, earning five best paper awards, an IEEE certification, and three international patents on low power design. Since 1997, he has participated in 18 EU-funded projects. His research focuses on multi/many-core architectures, NoC, low power design, and more.