Abstract
This paper proposes a system-level design methodology for the efficient exploration of the memory architecture from the energy-delay combined perspective. The aim is to find a sub-optimal configuration of the memory hierarchy without performing the exhaustive analysis of the parameters space
William Fornaciari
Associate Professor
William Fornaciari has published six books and over 200 papers, earning five best paper awards, an IEEE certification, and three international patents on low power design. Since 1997, he has participated in 18 EU-funded projects. His research focuses on multi/many-core architectures, NoC, low power design, and more.
Vittorio Zaccaria
Associate Professor
I am an associate professor at Politecnico di Milano and I have worked in embedded processor architecture R&D for one of the top semiconductor companies in the world. My group is currently working on topics related to embedded systems (hardware and software), security, cryptography, operating systems.