An Assembly-Level Execution-Time Model for Pipelined Architectures

Abstract

The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter-instruction effects. Such effects depend on the processor state and the pipeline behavior, and are related to the dynamic execution of assembly code. The paper proposes a mathematical model of the delays deriving from instruction dependencies and gives a statistical characterization of such timing overheads. The model has been validated on a commercial architecture, the Intel486, by means of timing analysis of a set of benchmarks, obtaining an error within 5%. This model can be seamlessly integrated with a static energy consumption model in order to obtain precise software power and energy estimations

Publication
Proc. IEE/ACM International Conference on Computer Aided Design 2001
Carlo Brandolese
Carlo Brandolese
Assistant Professor

Carlo Brandolese is a researcher at the Department of Electronics and Information of the Politecnico di Milano and a consultant researcher at Cefriel Research Centre. His research interests are focused on design and low-power methodologies for embedded systems.

William Fornaciari
William Fornaciari
Associate Professor

William Fornaciari has published six books and over 200 papers, earning five best paper awards, an IEEE certification, and three international patents on low power design. Since 1997, he has participated in 18 EU-funded projects. His research focuses on multi/many-core architectures, NoC, low power design, and more.