Abstract
This paper presents a parametric area estimation methodology ‘at SystemC level for FPGA-based designs. The ap proach is conceived to reduce the effort to adapt the area e6 timators to the evolutions of the EDA design environments. It coisists in identifying the subset of measures that can be derived form the system level description and that are also relevant at VHDL-RT level. Estimators’ parameters are then automatically derived from a set of benchmarks.
Carlo Brandolese
Assistant Professor
Carlo Brandolese is a researcher at the Department of Electronics and Information of the Politecnico di Milano and a consultant researcher at Cefriel Research Centre. His research interests are focused on design and low-power methodologies for embedded systems.
William Fornaciari
Associate Professor
William Fornaciari has published six books and over 200 papers, earning five best paper awards, an IEEE certification, and three international patents on low power design. Since 1997, he has participated in 18 EU-funded projects. His research focuses on multi/many-core architectures, NoC, low power design, and more.