A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures

Abstract

The execution of multiple multimedia applications on a modern Multi-Processor System-on-Chip (MPSoC) rises up the need of a Run-Time Management (RTM) layer to match hardware and application needs. This paper proposes a novel model for the run-time resource allocation problem taking into account both architectural and application standpoints. Our model considers clustered and non-clustered resources, migration and reconfiguration overheads, quality of service (QoS) and application priorities. A near optimal solution is computed focusing on spatial and computational constraints. Experiments reveal that our first implementation is able to manage tens of applications with an overhead of only fews milliseconds and a memory footprint of less than one hundred KB, thus suitable for usage on real systems.

Publication
Proceeding ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Davide Zoni
Davide Zoni
Associate Professor

Davide Zoni received the Master Degree in Computer Engineering in 2010 and the Ph.D. in Information Technology in 2014, both from Politecnico di Milano, Italy, where he holds a Post-Doc position at DEIB—Dipartimento di Elettronica Informazione e Bioingegneria. His research interests include RTL design and low-power optimizations for multi-cores with particular emphasis on cache coherence protocols, on-chip interconnect and hardware-based side-channel countermeasures.

William Fornaciari
William Fornaciari
Associate Professor

William Fornaciari has published six books and over 200 papers, earning five best paper awards, an IEEE certification, and three international patents on low power design. Since 1997, he has participated in 18 EU-funded projects. His research focuses on multi/many-core architectures, NoC, low power design, and more.