A cycle accurate simulation framework for asynchronous NoC design

Federico Terraneo, Davide Zoni, William Fornaciari

January 2013

Abstract

Abstract— Network-on-Chip (NoC) represents a flexible and scalable interconnection candidate for current and future multi- cores. In such a scenario power represents a major design obstacle, requiring accurate early-stage estimation for both cores and NoCs. In this perspective, Dynamic Frequency Scaling (DFS) techniques have been proposed as a flexible and scalable way to optimize the power-performance trade-off. However, there is a lack of tools that allow for an early-stage evaluation of different DFS solutions as well as asynchronous NoC. This work proposes a new cycle-accurate simulation framework supporting asynchronous NoC design, allowing also to assess heterogeneous and dynamic frequency schemes for NoC routers.

Type

Conference paper

Publication

System on Chip (SoC), 2013 International Symposium on

Federico Terraneo

Associate Professor

Federico Terraneo received his B.Sc. and M.Sc. degrees in computer engineering from the Politecnico di Milano, Milan, Italy, and his Ph.D. degree in Information Technology from Politecnico di Milano in 2015. Currently he holds a Postdoc position at Politecnico di Milano. His research interests include embedded systems and the application of principles of control theory to the design of software systems. Since 2008 he has been the main developer and maintainer of the Miosix embedded operating system.

Davide Zoni

Associate Professor

Davide Zoni received the Master Degree in Computer Engineering in 2010 and the Ph.D. in Information Technology in 2014, both from Politecnico di Milano, Italy, where he holds a Post-Doc position at DEIB—Dipartimento di Elettronica Informazione e Bioingegneria. His research interests include RTL design and low-power optimizations for multi-cores with particular emphasis on cache coherence protocols, on-chip interconnect and hardware-based side-channel countermeasures.