Abstract
While technology scaling allows to integrate more cores in the same chip, the complexity of current designs requires accurate and fast techniques to explore different trade-offs. Moreover, the increased power densities in current architectures highlight thermal issues as a first class design metric to be addressed. At the same time, the need to access to accurate models for the exploited actuators is of paramount importance, since their overheads can shadow the benefit of the proposed methodologies. This paper proposes a complete simulation framework for the assessment of run-time policies for thermal-performance and power-performance trade-offs optimization with two main improvements over the state of the art. First, it accurately models Dynamic Voltage and Frequency Scaling (DVFS) modules for both cores and NoC routers as well as a complete Globally Asynchronous Locally Synchronous (GALS) design paradigm and power gating support for crossabar and buffers in the NoC. Second, it accounts for the chip thermal dynamics as well as power and performance overheads for the actuators.
Federico Terraneo
Associate Professor
Federico Terraneo received his B.Sc. and M.Sc. degrees in computer engineering from the Politecnico di Milano, Milan, Italy, and his Ph.D. degree in Information Technology from Politecnico di Milano in 2015. Currently he holds a Postdoc position at Politecnico di Milano. His research interests include embedded systems and the application of principles of control theory to the design of software systems. Since 2008 he has been the main developer and maintainer of the Miosix embedded operating system.
Davide Zoni
Associate Professor
Davide Zoni received the Master Degree in Computer Engineering in 2010 and the Ph.D. in Information Technology in 2014, both from Politecnico di Milano, Italy, where he holds a Post-Doc position at DEIB—Dipartimento di Elettronica Informazione e Bioingegneria. His research interests include RTL design and low-power optimizations for multi-cores with particular emphasis on cache coherence protocols, on-chip interconnect and hardware-based side-channel countermeasures.
William Fornaciari
Associate Professor
William Fornaciari has published six books and over 200 papers, earning five best paper awards, an IEEE certification, and three international patents on low power design. Since 1997, he has participated in 18 EU-funded projects. His research focuses on multi/many-core architectures, NoC, low power design, and more.