One key innovation of the proposed approach consists in introducing a separation of concerns (where self-adaptivity and energy efficient strategies are specified aside from the application functionalities) promoted by the definition of a Domain Specific Language (DSL) inspired by aspect-oriented programming concepts for heterogeneous systems. The new DSL will be introduced for expressing the adaptivity/energy/performance strategies and to enforce at runtime application autotuning and resource and power management.
The goal is to support the parallelism, scalability and adaptability of a dynamic workload by exploiting the full system capabilities (including energy management) for emerging large-scale and extreme-scale systems, while reducing the Total Cost of Ownership (TCO) for companies and public organizations.
View ANTAREX official website.
- Stefano Cherubin
- Davide Gadioli
- Emanuele Vitali
- C Silvano et al. The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems. Proceedings of the ACM International Conference on Computing Frontiers, pp. 288-293, 2015
- C Silvano et al. AutoTuning and Adaptivity appRoach for Energy efficient eXascale HPC systems: the ANTAREX Approach. Design, Automation, and Test in Europe
- C Silvano et al. ANTAREX--AutoTuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems. IEEE 18th International Computational Science and Engineering (CSE), 2015
- Heterogeneous computing cores
- Memory architecture
- Runtime resource management
- Power monitoring and cooling
- Programming models
This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 671668 Visit MANGO official website
- J Flich et al. The MANGO FET-HPC Project: An Overview. 2015 IEEE 18th International on Computational Sciences and Engineering
- J Flich et al. Enabling HPC for QoS-sensitive applications: The MANGO approach. 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 702-70
- A Pupykina, G Agosta. Optimizing Memory Management in Deeply Heterogeneous HPC Accelerators. 46th International Conference on Parallel Processing Workshops (ICPPW), pp. 291-300, 2017
- J Flich et al. MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. 2017 Euromicro Conference on Digital System Design, Special Session on European Project in Digital System Design, pp. 478-485, Vienna 2017.
The M2DC server platform will enable customization and smooth adaptation to various types of applications, while advanced management strategies and system efficiency enhancements (SEE) will be used to achieve high levels of energy efficiency, performance, security and reliability. The M2DC middleware will provide a data centre capable abstraction of the underlying heterogeneity of the M2DC Server. On top of that it allows to deploy variable, optimized appliances including, e.g., photo finishing systems, IoT data processing, cloud computing and HPC.
View M2DC official website.
- Prof William Fornaciari
- Prof Giovanni Agosta
- Prof Carlo Brandolese
- Prof Gerardo Pelosi
- Prof Alessandro Barenghi
- Dr Federico Terraneo
- Dr Francesca Micol Rossi
- A Oleksiak et al. M2DC–Modular Microserver DataCentre with Heterogeneous Hardware. Microprocessors and Microsystems, 2017
- M Cecowski et al. The M2DC Project: Modular Microserver DataCentre. Euromicro Conference on Digital System Design (DSD), pp. 68-74, 2016
- MKA Oleksiak et al. Data centres for IoT applications: The M2DC approach. Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), 2016
- Lower certification costs
- Increased trustworthiness of wireless communication
- Better management of increasing complexity
- Reduced effort for verification and validation
- Lower total system costs
- Shorter time to market
- Increased market share
- A Agneessens et al. Safe cooperative CPS: A V2I traffic management scenario in the SafeCOP project. Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)
- G Agosta et al. V2I Cooperation for Traffic Management with SafeCop. Digital System Design (DSD), 2016 Euromicro Conference on, 621-627
This class of computing systems (Many-core Computing Fabric) promises to increase performance, scalability and flexibility if appropriate design and programming methodologies will be defined to exploit the high degree of parallelism exposed by the architecture. Other potential benefits of Many-core Computing Fabric include energy efficiency, improved silicon yield, and accounting for local process variations. To exploit these potential benefits, effective run-time power and resource management techniques are needed. With respect to conventional computing architectures, Many-core Computing Fabric offers some customisation capabilities to extend and/or configure at run-time the architectural template to address a variable workload.
The 2PARMA project (Jan 2010 - Dec 2012) focuses on the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable bytecode, run-time resource management policies and mechanisms as well as design space exploration methodologies for Many-core Computing Fabrics.
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- C Silvano et a. 2parma: parallel paradigms and run-time management techniques for many-core architectures. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 494-499, 2010
- C Silvano et al. Parallel programming and run-time resource management framework for many-core platforms: The 2parma approach. 6th Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011.
- G Ascheid et al. Parallel paradigms and run-time management techniques for many-core architectures. Interconnection Network Architecture on On-Chip. Multi-Chip Workshop, 2012
- C Silvano et al. Parallel paradigms and run-time management techniques for many-core architectures: The 2PARMA approach. 9th IEEE International Conference on Industrial Informatics (INDIN), 2011
- C Brandolese and W Fornaciari.Software Energy Optimization Through Fine-Grained Function-Level Voltage and Frequency Scaling. In International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'2012). Tampere, Finland, October 2012.
- K Grüttner et al. COMPLEX - COdesign and power Management in PLatform-based design space EXploration. In Proc. of the 15th Euromicro Conference on Digital System Design (DSD'2012). Cesme-Izmir, Turkey, September 2012.
- P Bellasi, W Betz, L M Marchi and W Fornaciari. A Step Toward Exploiting Task Affinity in Multi-core Architectures to Improve Determinism of Real-time Applications. In International Conference on Real-Time and Embedded Systems (RTES'2010). Singapore, November 2010.
- C Brandolese and L Rucco. A Genetic Approach for WSN Lifetime Maximization through Dynamic Linking and Management. In Proc. of the 7th ACM workshop on Performance Evaluation of Wireless Ad Hoc, Sensor, and Ubiquitous Networks (PE-WASUN'10). Bodrum, Turkey, pp. 99-100, 2010.
- P Bellasi et al. Queueing Network Models for Performance Evaluation of ZigBee-Based WSNs. In Alessandro Aldini, Marco Bernardo, Luciano Bononi and Vittorio Cortellessa (eds.). Computer Performance Engineering. Series LNCS, volume 6342, Springer Berlin/Heidelberg, pages 147-159, 201.
- P Bellasi et al. Constrained Power Management: Application to a Multimedia Mobile Platform. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE'10). Dresden, Germany, pp. 989–992, 2010.
- C Brandolese, W Fornaciari and L Rucco. A Lightweight Mechanism for Dynamic Linking in Wireless Sensor Networks. In IEEE Latin America Symposium on Circuits and Systems (LASCAS'10). Foz do Iguazu, Paranà, Brazil, February 2010.
- C Brandolese, W Fornaciari and D P Scarpazza. Source-Level Energy Estimation and Optimization of Embedded Software. In IEEE Latin America Symposium on Circuits and Systems (LASCAS'10). Foz do Iguazu, Paranà, Brazil, February 2010.
- W Fornaciari and P Bellasi. Cross-Layer Constrained Power Management: Application to a Multimedia Mobile Platform. In IEEE Latin America Symposium on Circuits and Systems (LASCAS'10). Foz do Iguazu, Paranà, Brazil, February 2010.
- P Bellasi, W Fornaciari and D Siorpaes. A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems. In Christian Müller-Schloer, Wolfgang Karl and Sami Yehia (eds.). Architecture of Computing Systems (ARCS'2010). Series LNCS, volume 5974, Springer Berlin/Heidelberg, pp. 37-48, 2010.
- P Bellasi et al. CPM: A Cross-Layer Framework to Efficiently Support Distributed Resources Management. In Workshop on Parallel Programming and Run-time Management for Many-core Architectures (PARMA'2010). Hannover, Germany, pp 293–298, February 2010
- P Bellasi, S Corbetta and W Fornaciari. Hierarchical Power Management. In Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP'2010). Dresden, Germany, March 2010.
- scaling up the number of applications per platform and the number of cores per chip
- in battery powered devices or
- switching to smaller technology nodes
View CONTREX official website.
- Ralph Görgen et al. CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties, 2016 Euromicro Conference on Digital System Design (DSD), Limassol, pp. 286-293, 2016.
- Carlo Brandolese, Luigi Rucco, William Fornaciari. An optimal model to partition the evolution of periodic tasks in wireless sensor networks. IEEE international symposium on a world of wireless mobile and multimedia networks. Sydney, Australia, June 2014
- Carlo Brandolese, Luigi Rucco, William Fornaciari. Optimal wakeups clustering for highly-efficient operation of WSNs periodic applications. IEEE international conference on information communication and embedded systems (ICICES), Chennai, Tamilnadu, India, February 2014
View HARPA official website.
- Davide Zoni et al. BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers. Journal of Parallel and Distributed Computing, January 2017.
- Davide Zoni and William Fornaciari. Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators. ACM Journal on Emerging Technologies in Computing Systems, Vol. 12, No. 3, Article 27, September 2015
- Davide Zoni, Federico Terraneo, and William Fornaciari. A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations. J. Signal Process. Syst. 83, 3, pp. 357-371, June 2016.
- Patrick Bellasi, Giuseppe Massari, and William Fornaciari. Effective Runtime Resource Management Using Linux Control Groups with the BarbequeRTRM Framework. ACM Trans. Embed. Comput. Syst. 14, 2, Article 39, March 2015.
- split compilation techniques that leverage component based SW engineering and provide binary portability (CLI standard) with no performance penalty
- standardized and open application programmers’ interfaces (API) for advanced multimedia stacks that support resource management and context awareness at component level
Read more information on OpenMediaPlatform here.
- Tartara M., Campanoni S., Agosta G., Reghizzi S.C. Just-in-time compilation on ARM processors. 2009
- Campanoni S., Agosta G., Crespi Reghizzi S., Di Biagio A. A highly flexible, parallel virtual machine: Design and experience of ILDJIT. Software: Practice and Experience, 2010
- G Agosta, M Cartron, A Miele. Fault tolerance. Smart Multicore Embedded Systems, pp. 81-101, 2013
TOISE proposes to address the secure tamper resistant solutions needed by the related embedded applications. Trusted Computing now in practise for the PC and workstation area provides a proven approach face to new attacks, by implementing a chain of authentication and integrity from the boot of the computing platform to the applications set up.
The aim is to maintain Europe as a worldwide player in the field of efficient implementation of secure integrated devices to address the future European applications. A large initiative is proposed to align a common European position in the area. Several of TOISE partners are participating to related standardisation working groups, such TOISE will allow to develop and promote European solutions in non-yet harmonised bodies. TOISE brings together European and manufacturing based Semiconductors such STMicroelectronics and Numonyx and Systems actors such Eads, Gemalto, Helenic Aerospace, Proton and Thales, to develop safe and secure solutions. SME develop enabling blocks as IP : Secure IC and Magillem Design. SME contribute to apply the technology to the related targeted applications : AZCom and TST. Cea Leti as security evaluation center performs some security tests. Seven research labs from the participating countries develop the further enabling research.
View TOISE official website.